mali_base_kernel.h

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/*
 *
 * (C) COPYRIGHT 2010-2016 ARM Limited. All rights reserved.
 *
 * This program is free software and is provided to you under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation, and any use by you of this program is subject to the terms
 * of such GNU licence.
 *
 * A copy of the licence is included with the program, and can also be obtained
 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 * Boston, MA  02110-1301, USA.
 *
 */





#ifndef _BASE_KERNEL_H_
#define _BASE_KERNEL_H_

#ifndef __user
#define __user
#endif

/* Support UK6 IOCTLS */
#define BASE_LEGACY_UK6_SUPPORT 1

/* Support UK7 IOCTLS */
/* NB: To support UK6 we also need to support UK7 */
#define BASE_LEGACY_UK7_SUPPORT 1

/* Support UK8 IOCTLS */
#define BASE_LEGACY_UK8_SUPPORT 1

/* Support UK9 IOCTLS */
#define BASE_LEGACY_UK9_SUPPORT 1

/* Support UK10_2 IOCTLS */
#define BASE_LEGACY_UK10_2_SUPPORT 1

/* Support UK10_4 IOCTLS */
#define BASE_LEGACY_UK10_4_SUPPORT 1

typedef struct base_mem_handle {
    struct {
        u64 handle;
    } basep;
} base_mem_handle;

#include "mali_base_mem_priv.h"
#include "mali_kbase_profiling_gator_api.h"
#include "mali_midg_coherency.h"
#include "mali_kbase_gpu_id.h"

/*
 * Dependency stuff, keep it private for now. May want to expose it if
 * we decide to make the number of semaphores a configurable
 * option.
 */
#define BASE_JD_ATOM_COUNT              256

#define BASEP_JD_SEM_PER_WORD_LOG2      5
#define BASEP_JD_SEM_PER_WORD           (1 << BASEP_JD_SEM_PER_WORD_LOG2)
#define BASEP_JD_SEM_WORD_NR(x)         ((x) >> BASEP_JD_SEM_PER_WORD_LOG2)
#define BASEP_JD_SEM_MASK_IN_WORD(x)    (1 << ((x) & (BASEP_JD_SEM_PER_WORD - 1)))
#define BASEP_JD_SEM_ARRAY_SIZE         BASEP_JD_SEM_WORD_NR(BASE_JD_ATOM_COUNT)

/* Set/reset values for a software event */
#define BASE_JD_SOFT_EVENT_SET             ((unsigned char)1)
#define BASE_JD_SOFT_EVENT_RESET           ((unsigned char)0)

#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3

#define BASE_MAX_COHERENT_GROUPS 16

#define BASE_DEBUG_FENCE_TIMEOUT 1

#if defined CDBG_ASSERT
#define LOCAL_ASSERT CDBG_ASSERT
#elif defined KBASE_DEBUG_ASSERT
#define LOCAL_ASSERT KBASE_DEBUG_ASSERT
#else
#error assert macro not defined!
#endif

#if defined PAGE_MASK
#define LOCAL_PAGE_LSB ~PAGE_MASK
#else
#include <osu/mali_osu.h>

#if defined OSU_CONFIG_CPU_PAGE_SIZE_LOG2
#define LOCAL_PAGE_LSB ((1ul << OSU_CONFIG_CPU_PAGE_SIZE_LOG2) - 1)
#else
#error Failed to find page size
#endif
#endif

typedef union kbase_pointer {
    void __user *value;   
    u32 compat_value; 
    u64 sizer;    
} kbase_pointer;

typedef u32 base_mem_alloc_flags;

enum {
/* IN */
    BASE_MEM_PROT_CPU_RD = (1U << 0),      
    BASE_MEM_PROT_CPU_WR = (1U << 1),      
    BASE_MEM_PROT_GPU_RD = (1U << 2),      
    BASE_MEM_PROT_GPU_WR = (1U << 3),      
    BASE_MEM_PROT_GPU_EX = (1U << 4),      
    /* BASE_MEM_HINT flags have been removed, but their values are reserved
     * for backwards compatibility with older user-space drivers. The values
     * can be re-used once support for r5p0 user-space drivers is removed,
     * presumably in r7p0.
     *
     * RESERVED: (1U << 5)
     * RESERVED: (1U << 6)
     * RESERVED: (1U << 7)
     * RESERVED: (1U << 8)
     */

    BASE_MEM_GROW_ON_GPF = (1U << 9),      
    BASE_MEM_COHERENT_SYSTEM = (1U << 10), 
    BASE_MEM_COHERENT_LOCAL = (1U << 11),  
    BASE_MEM_CACHED_CPU = (1U << 12),      
/* IN/OUT */
    BASE_MEM_SAME_VA = (1U << 13), 
/* OUT */
    BASE_MEM_NEED_MMAP = (1U << 14), 
/* IN */
    BASE_MEM_COHERENT_SYSTEM_REQUIRED = (1U << 15), 
    BASE_MEM_SECURE = (1U << 16),          
    BASE_MEM_DONT_NEED = (1U << 17),       
    BASE_MEM_IMPORT_SHARED = (1U << 18),   
};

#define BASE_MEM_FLAGS_NR_BITS 19

#define BASE_MEM_FLAGS_OUTPUT_MASK BASE_MEM_NEED_MMAP

#define BASE_MEM_FLAGS_INPUT_MASK \
    (((1 << BASE_MEM_FLAGS_NR_BITS) - 1) & ~BASE_MEM_FLAGS_OUTPUT_MASK)

#define BASE_MEM_FLAGS_MODIFIABLE \
    (BASE_MEM_DONT_NEED | BASE_MEM_COHERENT_SYSTEM | \
     BASE_MEM_COHERENT_LOCAL)

typedef enum base_mem_import_type {
    BASE_MEM_IMPORT_TYPE_INVALID = 0,
    BASE_MEM_IMPORT_TYPE_UMP = 1,
    BASE_MEM_IMPORT_TYPE_UMM = 2,
    BASE_MEM_IMPORT_TYPE_USER_BUFFER = 3
} base_mem_import_type;

struct base_mem_import_user_buffer {
    kbase_pointer ptr;
    u64 length;
};

#define BASE_MEM_INVALID_HANDLE ((base_mem_handle) { {BASEP_MEM_INVALID_HANDLE} })

#define BASE_MEM_WRITE_ALLOC_PAGES_HANDLE ((base_mem_handle) { {BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE} })

#define BASEP_MEM_INVALID_HANDLE               (0ull  << 12)
#define BASE_MEM_MMU_DUMP_HANDLE               (1ull  << 12)
#define BASE_MEM_TRACE_BUFFER_HANDLE           (2ull  << 12)
#define BASE_MEM_MAP_TRACKING_HANDLE           (3ull  << 12)
#define BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE     (4ull  << 12)
/* reserved handles ..-64<<PAGE_SHIFT> for future special handles */
#define BASE_MEM_COOKIE_BASE                   (64ul  << 12)
#define BASE_MEM_FIRST_FREE_ADDRESS            ((BITS_PER_LONG << 12) + \
                        BASE_MEM_COOKIE_BASE)

/* Mask to detect 4GB boundary alignment */
#define BASE_MEM_MASK_4GB  0xfffff000UL


/* Bit mask of cookies used for for memory allocation setup */
#define KBASE_COOKIE_MASK  ~1UL /* bit 0 is reserved */


typedef enum base_backing_threshold_status {
    BASE_BACKING_THRESHOLD_OK = 0,              
    BASE_BACKING_THRESHOLD_ERROR_NOT_GROWABLE = -1,     
    BASE_BACKING_THRESHOLD_ERROR_OOM = -2,          
    BASE_BACKING_THRESHOLD_ERROR_INVALID_ARGUMENTS = -4 
} base_backing_threshold_status;

typedef struct base_syncset {
    struct basep_syncset basep_sset;
} base_syncset;

typedef struct base_import_handle {
    struct {
        u64 handle;
    } basep;
} base_import_handle;

typedef int platform_fence_type;
#define INVALID_PLATFORM_FENCE ((platform_fence_type)-1)

typedef struct base_stream {
    struct {
        int fd;
    } basep;
} base_stream;

typedef struct base_fence {
    struct {
        int fd;
        int stream_fd;
    } basep;
} base_fence;

typedef struct base_jd_udata {
    u64 blob[2];     
} base_jd_udata;

struct base_mem_aliasing_info {
    base_mem_handle handle;
    u64 offset;
    u64 length;
};

struct base_jit_alloc_info {
    u64 gpu_alloc_addr;
    u64 va_pages;
    u64 commit_pages;
    u64 extent;
    u8 id;
};

typedef u8 base_jd_dep_type;


#define BASE_JD_DEP_TYPE_INVALID  (0)       
#define BASE_JD_DEP_TYPE_DATA     (1U << 0) 
#define BASE_JD_DEP_TYPE_ORDER    (1U << 1) 
typedef u32 base_jd_core_req;

/* Requirements that come from the HW */

#define BASE_JD_REQ_DEP ((base_jd_core_req)0)

#define BASE_JD_REQ_FS  ((base_jd_core_req)1 << 0)

#define BASE_JD_REQ_CS  ((base_jd_core_req)1 << 1)
#define BASE_JD_REQ_T   ((base_jd_core_req)1 << 2)   
#define BASE_JD_REQ_CF  ((base_jd_core_req)1 << 3)   
#define BASE_JD_REQ_V   ((base_jd_core_req)1 << 4)   
/* SW-only requirements - the HW does not expose these as part of the job slot capabilities */

/* Requires fragment job with AFBC encoding */
#define BASE_JD_REQ_FS_AFBC  ((base_jd_core_req)1 << 13)

#define BASE_JD_REQ_EVENT_COALESCE ((base_jd_core_req)1 << 5)

#define BASE_JD_REQ_COHERENT_GROUP  ((base_jd_core_req)1 << 6)

#define BASE_JD_REQ_PERMON               ((base_jd_core_req)1 << 7)

#define BASE_JD_REQ_EXTERNAL_RESOURCES   ((base_jd_core_req)1 << 8)

#define BASE_JD_REQ_SOFT_JOB        ((base_jd_core_req)1 << 9)

#define BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME      (BASE_JD_REQ_SOFT_JOB | 0x1)
#define BASE_JD_REQ_SOFT_FENCE_TRIGGER          (BASE_JD_REQ_SOFT_JOB | 0x2)
#define BASE_JD_REQ_SOFT_FENCE_WAIT             (BASE_JD_REQ_SOFT_JOB | 0x3)

#define BASE_JD_REQ_SOFT_REPLAY                 (BASE_JD_REQ_SOFT_JOB | 0x4)

#define BASE_JD_REQ_SOFT_EVENT_WAIT             (BASE_JD_REQ_SOFT_JOB | 0x5)
#define BASE_JD_REQ_SOFT_EVENT_SET              (BASE_JD_REQ_SOFT_JOB | 0x6)
#define BASE_JD_REQ_SOFT_EVENT_RESET            (BASE_JD_REQ_SOFT_JOB | 0x7)

#define BASE_JD_REQ_SOFT_DEBUG_COPY             (BASE_JD_REQ_SOFT_JOB | 0x8)

#define BASE_JD_REQ_SOFT_JIT_ALLOC              (BASE_JD_REQ_SOFT_JOB | 0x9)

#define BASE_JD_REQ_SOFT_JIT_FREE               (BASE_JD_REQ_SOFT_JOB | 0xa)

#define BASE_JD_REQ_SOFT_EXT_RES_MAP            (BASE_JD_REQ_SOFT_JOB | 0xb)

#define BASE_JD_REQ_SOFT_EXT_RES_UNMAP          (BASE_JD_REQ_SOFT_JOB | 0xc)

#define BASE_JD_REQ_ONLY_COMPUTE    ((base_jd_core_req)1 << 10)

#define BASE_JD_REQ_SPECIFIC_COHERENT_GROUP ((base_jd_core_req)1 << 11)

#define BASE_JD_REQ_EVENT_ONLY_ON_FAILURE   ((base_jd_core_req)1 << 12)

#define BASEP_JD_REQ_EVENT_NEVER ((base_jd_core_req)1 << 14)

#define BASE_JD_REQ_SKIP_CACHE_START ((base_jd_core_req)1 << 15)

#define BASE_JD_REQ_SKIP_CACHE_END ((base_jd_core_req)1 << 16)

#define BASEP_JD_REQ_RESERVED \
    (~(BASE_JD_REQ_ATOM_TYPE | BASE_JD_REQ_EXTERNAL_RESOURCES | \
    BASE_JD_REQ_EVENT_ONLY_ON_FAILURE | BASEP_JD_REQ_EVENT_NEVER | \
    BASE_JD_REQ_EVENT_COALESCE | \
    BASE_JD_REQ_COHERENT_GROUP | BASE_JD_REQ_SPECIFIC_COHERENT_GROUP | \
    BASE_JD_REQ_FS_AFBC | BASE_JD_REQ_PERMON | \
    BASE_JD_REQ_SKIP_CACHE_START | BASE_JD_REQ_SKIP_CACHE_END))

#define BASE_JD_REQ_ATOM_TYPE \
    (BASE_JD_REQ_FS | BASE_JD_REQ_CS | BASE_JD_REQ_T | BASE_JD_REQ_CF | \
    BASE_JD_REQ_V | BASE_JD_REQ_SOFT_JOB | BASE_JD_REQ_ONLY_COMPUTE)

#define BASE_JD_REQ_SOFT_JOB_TYPE (BASE_JD_REQ_SOFT_JOB | 0x1f)

/*
 * Returns non-zero value if core requirements passed define a soft job or
 * a dependency only job.
 */
#define BASE_JD_REQ_SOFT_JOB_OR_DEP(core_req) \
    ((core_req & BASE_JD_REQ_SOFT_JOB) || \
    (core_req & BASE_JD_REQ_ATOM_TYPE) == BASE_JD_REQ_DEP)

enum kbase_atom_coreref_state {
    KBASE_ATOM_COREREF_STATE_NO_CORES_REQUESTED,
    KBASE_ATOM_COREREF_STATE_WAITING_FOR_REQUESTED_CORES,
    KBASE_ATOM_COREREF_STATE_RECHECK_AFFINITY,
    KBASE_ATOM_COREREF_STATE_CHECK_AFFINITY_VIOLATIONS,
    KBASE_ATOM_COREREF_STATE_READY
};

/*
 * Base Atom priority
 *
 * Only certain priority levels are actually implemented, as specified by the
 * BASE_JD_PRIO_<...> definitions below. It is undefined to use a priority
 * level that is not one of those defined below.
 *
 * Priority levels only affect scheduling between atoms of the same type within
 * a base context, and only after the atoms have had dependencies resolved.
 * Fragment atoms does not affect non-frament atoms with lower priorities, and
 * the other way around. For example, a low priority atom that has had its
 * dependencies resolved might run before a higher priority atom that has not
 * had its dependencies resolved.
 *
 * The scheduling between base contexts/processes and between atoms from
 * different base contexts/processes is unaffected by atom priority.
 *
 * The atoms are scheduled as follows with respect to their priorities:
 * - Let atoms 'X' and 'Y' be for the same job slot who have dependencies
 *   resolved, and atom 'X' has a higher priority than atom 'Y'
 * - If atom 'Y' is currently running on the HW, then it is interrupted to
 *   allow atom 'X' to run soon after
 * - If instead neither atom 'Y' nor atom 'X' are running, then when choosing
 *   the next atom to run, atom 'X' will always be chosen instead of atom 'Y'
 * - Any two atoms that have the same priority could run in any order with
 *   respect to each other. That is, there is no ordering constraint between
 *   atoms of the same priority.
 */
typedef u8 base_jd_prio;

/* Medium atom priority. This is a priority higher than BASE_JD_PRIO_LOW */
#define BASE_JD_PRIO_MEDIUM  ((base_jd_prio)0)
/* High atom priority. This is a priority higher than BASE_JD_PRIO_MEDIUM and
 * BASE_JD_PRIO_LOW */
#define BASE_JD_PRIO_HIGH    ((base_jd_prio)1)
/* Low atom priority. */
#define BASE_JD_PRIO_LOW     ((base_jd_prio)2)

/* Count of the number of priority levels. This itself is not a valid
 * base_jd_prio setting */
#define BASE_JD_NR_PRIO_LEVELS 3

enum kbase_jd_atom_state {
    KBASE_JD_ATOM_STATE_UNUSED,
    KBASE_JD_ATOM_STATE_QUEUED,
    KBASE_JD_ATOM_STATE_IN_JS,
    KBASE_JD_ATOM_STATE_HW_COMPLETED,
    KBASE_JD_ATOM_STATE_COMPLETED
};

typedef u8 base_atom_id; 
struct base_dependency {
    base_atom_id  atom_id;               
    base_jd_dep_type dependency_type;    
};

/* This structure has changed since UK 10.2 for which base_jd_core_req was a u16 value.
 * In order to keep the size of the structure same, padding field has been adjusted
 * accordingly and core_req field of a u32 type (to which UK 10.3 base_jd_core_req defines)
 * is added at the end of the structure. Place in the structure previously occupied by u16 core_req
 * is kept but renamed to compat_core_req and as such it can be used in ioctl call for job submission
 * as long as UK 10.2 legacy is supported. Once when this support ends, this field can be left
 * for possible future use. */
typedef struct base_jd_atom_v2 {
    u64 jc;             
    struct base_jd_udata udata;         
    kbase_pointer extres_list;      
    u16 nr_extres;              
    u16 compat_core_req;                
    struct base_dependency pre_dep[2];  
    base_atom_id atom_number;       
    base_jd_prio prio;                  
    u8 device_nr;               
    u8 padding[1];
    base_jd_core_req core_req;          
} base_jd_atom_v2;

#ifdef BASE_LEGACY_UK6_SUPPORT
struct base_jd_atom_v2_uk6 {
    u64 jc;             
    struct base_jd_udata udata;         
    kbase_pointer extres_list;      
    u16 nr_extres;              
    u16 core_req;                       
    base_atom_id pre_dep[2]; 
    base_atom_id atom_number;       
    base_jd_prio prio;          
    u8 device_nr;               
    u8 padding[7];
};
#endif /* BASE_LEGACY_UK6_SUPPORT */

typedef enum base_external_resource_access {
    BASE_EXT_RES_ACCESS_SHARED,
    BASE_EXT_RES_ACCESS_EXCLUSIVE
} base_external_resource_access;

typedef struct base_external_resource {
    u64 ext_resource;
} base_external_resource;


#define BASE_EXT_RES_COUNT_MAX 10

struct base_external_resource_list {
    u64 count;
    struct base_external_resource ext_res[1];
};

struct base_jd_debug_copy_buffer {
    u64 address;
    u64 size;
    struct base_external_resource extres;
};

static inline void base_jd_atom_dep_set(struct base_dependency *dep,
        base_atom_id id, base_jd_dep_type dep_type)
{
    LOCAL_ASSERT(dep != NULL);

    /*
     * make sure we don't set not allowed combinations
     * of atom_id/dependency_type.
     */
    LOCAL_ASSERT((id == 0 && dep_type == BASE_JD_DEP_TYPE_INVALID) ||
            (id > 0 && dep_type != BASE_JD_DEP_TYPE_INVALID));

    dep->atom_id = id;
    dep->dependency_type = dep_type;
}

static inline void base_jd_atom_dep_copy(struct base_dependency *dep,
        const struct base_dependency *from)
{
    LOCAL_ASSERT(dep != NULL);

    base_jd_atom_dep_set(dep, from->atom_id, from->dependency_type);
}

static inline void base_jd_fence_trigger_setup_v2(struct base_jd_atom_v2 *atom, struct base_fence *fence)
{
    LOCAL_ASSERT(atom);
    LOCAL_ASSERT(fence);
    LOCAL_ASSERT(fence->basep.fd == INVALID_PLATFORM_FENCE);
    LOCAL_ASSERT(fence->basep.stream_fd >= 0);
    atom->jc = (uintptr_t) fence;
    atom->core_req = BASE_JD_REQ_SOFT_FENCE_TRIGGER;
}

static inline void base_jd_fence_wait_setup_v2(struct base_jd_atom_v2 *atom, struct base_fence *fence)
{
    LOCAL_ASSERT(atom);
    LOCAL_ASSERT(fence);
    LOCAL_ASSERT(fence->basep.fd >= 0);
    atom->jc = (uintptr_t) fence;
    atom->core_req = BASE_JD_REQ_SOFT_FENCE_WAIT;
}

static inline void base_external_resource_init(struct base_external_resource *res, struct base_import_handle handle, base_external_resource_access access)
{
    u64 address;

    address = handle.basep.handle;

    LOCAL_ASSERT(res != NULL);
    LOCAL_ASSERT(0 == (address & LOCAL_PAGE_LSB));
    LOCAL_ASSERT(access == BASE_EXT_RES_ACCESS_SHARED || access == BASE_EXT_RES_ACCESS_EXCLUSIVE);

    res->ext_resource = address | (access & LOCAL_PAGE_LSB);
}

enum {
    BASE_JD_SW_EVENT_KERNEL = (1u << 15), 
    BASE_JD_SW_EVENT = (1u << 14), 
    BASE_JD_SW_EVENT_SUCCESS = (1u << 13), 
    BASE_JD_SW_EVENT_JOB = (0u << 11), 
    BASE_JD_SW_EVENT_BAG = (1u << 11), 
    BASE_JD_SW_EVENT_INFO = (2u << 11), 
    BASE_JD_SW_EVENT_RESERVED = (3u << 11), 
    BASE_JD_SW_EVENT_TYPE_MASK = (3u << 11)     
};

typedef enum base_jd_event_code {
    /* HW defined exceptions */

    BASE_JD_EVENT_RANGE_HW_NONFAULT_START = 0,

    /* non-fatal exceptions */
    BASE_JD_EVENT_NOT_STARTED = 0x00, 
    BASE_JD_EVENT_DONE = 0x01,
    BASE_JD_EVENT_STOPPED = 0x03,     
    BASE_JD_EVENT_TERMINATED = 0x04,  
    BASE_JD_EVENT_ACTIVE = 0x08,      
    BASE_JD_EVENT_RANGE_HW_NONFAULT_END = 0x40,

    BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_START = 0x40,

    /* job exceptions */
    BASE_JD_EVENT_JOB_CONFIG_FAULT = 0x40,
    BASE_JD_EVENT_JOB_POWER_FAULT = 0x41,
    BASE_JD_EVENT_JOB_READ_FAULT = 0x42,
    BASE_JD_EVENT_JOB_WRITE_FAULT = 0x43,
    BASE_JD_EVENT_JOB_AFFINITY_FAULT = 0x44,
    BASE_JD_EVENT_JOB_BUS_FAULT = 0x48,
    BASE_JD_EVENT_INSTR_INVALID_PC = 0x50,
    BASE_JD_EVENT_INSTR_INVALID_ENC = 0x51,
    BASE_JD_EVENT_INSTR_TYPE_MISMATCH = 0x52,
    BASE_JD_EVENT_INSTR_OPERAND_FAULT = 0x53,
    BASE_JD_EVENT_INSTR_TLS_FAULT = 0x54,
    BASE_JD_EVENT_INSTR_BARRIER_FAULT = 0x55,
    BASE_JD_EVENT_INSTR_ALIGN_FAULT = 0x56,
    BASE_JD_EVENT_DATA_INVALID_FAULT = 0x58,
    BASE_JD_EVENT_TILE_RANGE_FAULT = 0x59,
    BASE_JD_EVENT_STATE_FAULT = 0x5A,
    BASE_JD_EVENT_OUT_OF_MEMORY = 0x60,
    BASE_JD_EVENT_UNKNOWN = 0x7F,

    /* GPU exceptions */
    BASE_JD_EVENT_DELAYED_BUS_FAULT = 0x80,
    BASE_JD_EVENT_SHAREABILITY_FAULT = 0x88,

    /* MMU exceptions */
    BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL1 = 0xC1,
    BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL2 = 0xC2,
    BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL3 = 0xC3,
    BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL4 = 0xC4,
    BASE_JD_EVENT_PERMISSION_FAULT = 0xC8,
    BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL1 = 0xD1,
    BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL2 = 0xD2,
    BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL3 = 0xD3,
    BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL4 = 0xD4,
    BASE_JD_EVENT_ACCESS_FLAG = 0xD8,

    /* SW defined exceptions */
    BASE_JD_EVENT_MEM_GROWTH_FAILED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000,
    BASE_JD_EVENT_TIMED_OUT     = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x001,
    BASE_JD_EVENT_JOB_CANCELLED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002,
    BASE_JD_EVENT_JOB_INVALID   = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003,
    BASE_JD_EVENT_PM_EVENT      = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x004,
    BASE_JD_EVENT_FORCE_REPLAY  = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x005,

    BASE_JD_EVENT_BAG_INVALID   = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_BAG | 0x003,

    BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_RESERVED | 0x3FF,

    BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | 0x000,

    BASE_JD_EVENT_PROGRESS_REPORT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_JOB | 0x000,
    BASE_JD_EVENT_BAG_DONE = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_BAG | 0x000,
    BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_INFO | 0x000,

    BASE_JD_EVENT_RANGE_SW_SUCCESS_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_RESERVED | 0x3FF,

    BASE_JD_EVENT_RANGE_KERNEL_ONLY_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | 0x000,
    BASE_JD_EVENT_REMOVED_FROM_NEXT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x000,

    BASE_JD_EVENT_RANGE_KERNEL_ONLY_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_RESERVED | 0x3FF
} base_jd_event_code;

typedef struct base_jd_event_v2 {
    base_jd_event_code event_code;  
    base_atom_id atom_number;       
    struct base_jd_udata udata;     
} base_jd_event_v2;

#define BASE_CPU_GPU_CACHE_LINE_PADDING (36)


typedef struct base_dump_cpu_gpu_counters {
    u64 system_time;
    u64 cycle_counter;
    u64 sec;
    u32 usec;
    u8 padding[BASE_CPU_GPU_CACHE_LINE_PADDING];
} base_dump_cpu_gpu_counters;



#define GPU_MAX_JOB_SLOTS 16

#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3

#define BASE_MAX_COHERENT_GROUPS 16

struct mali_base_gpu_core_props {
    u32 product_id;

    u16 version_status;

    u16 minor_revision;

    u16 major_revision;

    u16 padding;

    u32 gpu_speed_mhz;

    u32 gpu_freq_khz_max;
    u32 gpu_freq_khz_min;

    u32 log2_program_counter_size;

    u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];

    u64 gpu_available_memory_size;
};

struct mali_base_gpu_l2_cache_props {
    u8 log2_line_size;
    u8 log2_cache_size;
    u8 num_l2_slices; /* Number of L2C slices. 1 or higher */
    u8 padding[5];
};

struct mali_base_gpu_tiler_props {
    u32 bin_size_bytes; /* Max is 4*2^15 */
    u32 max_active_levels;  /* Max is 2^15 */
};

struct mali_base_gpu_thread_props {
    u32 max_threads;            /* Max. number of threads per core */
    u32 max_workgroup_size;     /* Max. number of threads per workgroup */
    u32 max_barrier_size;       /* Max. number of threads that can synchronize on a simple barrier */
    u16 max_registers;          /* Total size [1..65535] of the register file available per core. */
    u8  max_task_queue;         /* Max. tasks [1..255] which may be sent to a core before it becomes blocked. */
    u8  max_thread_group_split; /* Max. allowed value [1..15] of the Thread Group Split field. */
    u8  impl_tech;              /* 0 = Not specified, 1 = Silicon, 2 = FPGA, 3 = SW Model/Emulation */
    u8  padding[7];
};

struct mali_base_gpu_coherent_group {
    u64 core_mask;         
    u16 num_cores;         
    u16 padding[3];
};

struct mali_base_gpu_coherent_group_info {
    u32 num_groups;

    u32 num_core_groups;

    u32 coherency;

    u32 padding;

    struct mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS];
};

struct gpu_raw_gpu_props {
    u64 shader_present;
    u64 tiler_present;
    u64 l2_present;
    u64 stack_present;

    u32 l2_features;
    u32 suspend_size; /* API 8.2+ */
    u32 mem_features;
    u32 mmu_features;

    u32 as_present;

    u32 js_present;
    u32 js_features[GPU_MAX_JOB_SLOTS];
    u32 tiler_features;
    u32 texture_features[3];

    u32 gpu_id;

    u32 thread_max_threads;
    u32 thread_max_workgroup_size;
    u32 thread_max_barrier_size;
    u32 thread_features;

    /*
     * Note: This is the _selected_ coherency mode rather than the
     * available modes as exposed in the coherency_features register.
     */
    u32 coherency_mode;
};

typedef struct mali_base_gpu_props {
    struct mali_base_gpu_core_props core_props;
    struct mali_base_gpu_l2_cache_props l2_props;
    u64 unused_1; /* keep for backwards compatibility */
    struct mali_base_gpu_tiler_props tiler_props;
    struct mali_base_gpu_thread_props thread_props;

    struct gpu_raw_gpu_props raw_props;

    struct mali_base_gpu_coherent_group_info coherency_info;
} base_gpu_props;

enum base_context_create_flags {
    BASE_CONTEXT_CREATE_FLAG_NONE = 0,

    BASE_CONTEXT_CCTX_EMBEDDED = (1u << 0),

    BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED = (1u << 1)
};

#define BASE_CONTEXT_CREATE_ALLOWED_FLAGS \
    (((u32)BASE_CONTEXT_CCTX_EMBEDDED) | \
      ((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED))

#define BASE_CONTEXT_CREATE_KERNEL_FLAGS \
    ((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED)

/*
 * Private flags used on the base context
 *
 * These start at bit 31, and run down to zero.
 *
 * They share the same space as @ref base_context_create_flags, and so must
 * not collide with them.
 */
#define BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED ((u32)(1 << 31))

typedef struct base_jd_replay_payload {
    u64 tiler_jc_list;

    u64 fragment_jc;

    u64 tiler_heap_free;

    u16 fragment_hierarchy_mask;

    u16 tiler_hierarchy_mask;

    u32 hierarchy_default_weight;

    base_jd_core_req tiler_core_req;

    base_jd_core_req fragment_core_req;
} base_jd_replay_payload;

#ifdef BASE_LEGACY_UK10_2_SUPPORT
typedef struct base_jd_replay_payload_uk10_2 {
    u64 tiler_jc_list;
    u64 fragment_jc;
    u64 tiler_heap_free;
    u16 fragment_hierarchy_mask;
    u16 tiler_hierarchy_mask;
    u32 hierarchy_default_weight;
    u16 tiler_core_req;
    u16 fragment_core_req;
    u8 padding[4];
} base_jd_replay_payload_uk10_2;
#endif /* BASE_LEGACY_UK10_2_SUPPORT */

typedef struct base_jd_replay_jc {
    u64 next;

    u64 jc;

} base_jd_replay_jc;

/* Maximum number of jobs allowed in a fragment chain in the payload of a
 * replay job */
#define BASE_JD_REPLAY_F_CHAIN_JOB_LIMIT 256

typedef struct base_profiling_controls {
    u32 profiling_controls[FBDUMP_CONTROL_MAX];
} base_profiling_controls;

/* Enable additional tracepoints for latency measurements (TL_ATOM_READY,
 * TL_ATOM_DONE, TL_ATOM_PRIO_CHANGE, TL_ATOM_EVENT_POST) */
#define BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS (1 << 0)

/* Indicate that job dumping is enabled. This could affect certain timers
 * to account for the performance impact. */
#define BASE_TLSTREAM_JOB_DUMPING_ENABLED (1 << 1)

#define BASE_TLSTREAM_FLAGS_MASK (BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS | \
        BASE_TLSTREAM_JOB_DUMPING_ENABLED)

#endif              /* _BASE_KERNEL_H_ */